A test apparatus such as this is illustrated by way of example in FIG. 2, and is used, for example, in order to test main memories of electronic circuit units (chips) with specific test modes (TM). The ACTM test mode (advanced compression test mode) is known, for example, as one such test mode. The advantages of a test mode such as this, are, on the one hand, that the circuit unit to be tested is tested internally by means of 16 I/O connecting pins, thus saving test time, and on the other hand that a test comparison is carried out internally, that is to say read and expected data or actual data streams and nominal data streams are compared internally.
Furthermore, data compression is advantageously carried out in a compression device to form 1 bit. This compressed test information is then emitted via a single I/O connecting pin.
This makes it possible to use conventional test apparatuses to determine whether a circuit unit to be tested has a fault, or whether it is operating without any faults. If only a single fault occurs during the course of a test on the circuit unit to be tested, then a test result signal which is compressed to 1 bit is set such that it indicates faulty operation of the circuit unit to be tested.
However, one disadvantageous feature is that it is not possible to determine a location at which and/or the time during the test at which a fault was found in the circuit unit to be tested.
Furthermore, in the case of so-called DDR memory modules (DDR=double data rate), each data access always results in even-numbered data and odd-numbered data, which is respectively read and written on the rising and falling clock flanks. If the circuit unit to be tested is operated internally with a length of 16 bits, then 32 bits are in each case produced on reading and writing, that is to say 16 bits of odd-numbered data and 16 bits of even-numbered data, which are then subsequently compressed in the compression device to form 1 bit of the test result signal. This compressed test information is conventionally emitted via an I/O connecting pin of the test apparatus.
One major disadvantage of conventional test apparatuses is therefore that they do not produce exact fault association. If, for example 32-bit data streams are compressed to form a test result signal comprising 1 bit, then, disadvantageously, it is no longer possible to locate an exact fault address. This disadvantageously means that correct physical fault analysis is no longer possible, even though this is required when the circuit unit to be tested is being analyzed or broken down.
During the production of circuit units, all that is important is to know whether the circuit unit has no faults (that is to say “pass”) or has faults (that is to say “fail”). The exact fault addresses are, however, critical for localization of the circuit unit to be tested for fault analysis purposes.
In order to solve this problem, it has been proposed that the corresponding ACTM test, which involves 32:1 compression, be rewritten to form a test without ACTM, in order that the circuit unit to be tested is tested without any compression. However, this results in the disadvantage that it involves additional complexity for writing a new test, that is to say additional programming effort.
A further disadvantage is that a new fault source can occur during conversion of a test to a non-ACTM test. An additional disadvantage is that a test such as this requires a test set that is not the same as that for an ACTM test, so that data is read and written via all of the I/O connecting pins. A final disadvantage of a test such as this is that the test time is increased, and that the tests are tested in their basic organization (×4, ×8, or ×16).